FPGA implementation of variable delay filters based on Farrow structure

U ovom radu opisani su filtri s varijabilnim kašnjenjem i razvijen je model filtra s varijabilnim kašnjenjem koji koristi Farrow strukturu te je napravljena njegova implementacija na razvojnom sustavu Zedboard. Model podržava maksimalan red filtra 10. U svrhu usporedbe razvijen je i model filtra s varijabilnim kašnjenjem koji koristi CIC interpolator. Testiranje nad nekoliko ispitnih signala pokazalo je da Farrow filtar daje rezultate bliže idealnima i koristi manje odsječaka programabilne logike, no za razliku od filtra sa CIC interpolatorom koristi DSP ćelije.In this thesis variable delay filters are described and a model of variable delay filter which uses Farrow structure is developed in VHDL and implemented on ZedBoard development board. The model supports maximum filter order of 10. Another variable delay filter which uses CIC interpolator is developed for comparison. The results show that the Farrow filter gives the results closer to ideal than the filter with CIC interpolator and uses less programmable logic slices. However, the filter with CIC interpolator does not use DSP slices