FPGA implementation of JPEG coder

U radu je opisana izrada i implementacija JPEG kodera zasnovanog na FPGA tehnologiji. Objašnjene su sve tehnologije potrebne za rad sustava, te postupak dizajniranja i funkcionalnosti svakog pojedinog modula. Nad sustavom su izvršena mjerenja, u kojima su se mjerila brzina obrade slike, te postignuti omjer kompresije za različite faktore kvalitete slike. Sustav se dizajnirao u Vivado razvojnom okruženju na Zynq-7000 SoC-u, gdje je procesor unosio konfiguracijske parametre a hardverski sustav vršio obradu slike. Rad sustava testiran je na više različitih slika, gdje se pokazalo da sustav ispunjava sve zadatke propisane JPEG normomThe paper describes the development and implementation of the JPEG coder based on the FPGA. All the technologies needed to operate the system, as well as the design and functionality of each module are explained. Measurements were performed over the system, measuring the speed of the image processing, and the compression ratio achieved for different image quality factors. The system was designed in the Vivado development environment on the Zynq-7000 SoC, where the processor introduced configuration parameters, and the hardware system processed the image. The system operation was tested on several different images, where it was shown that the system fulfilled all the tasks prescribed by the JPEG standard