Task-parallel programs inefficiently utilize the cache hierarchy due to the presence of dead blocks in caches. Dead blocks may occupy cache space in multiple cache levels for a long time without providing any utility until they are finally evicted. Existing dead-block prediction schemes take decisions locally for each cache level and do not efficiently manage the entire cache hierarchy. This article introduces runtime-orchestrated global dead-block management, in which static and dynamic information about tasks available to the runtime system is used to effectively detect and manage dead blocks across the cache hierarchy. In the proposed global management schemes, static information (e.g., when tasks start/finish, and what data regions task...
This dissertation analyzes a way to improve cache performance via active management of a target cach...
Abstract—While many block replacement algorithms for buffer caches have been proposed to address the...
The performance of cache memories relies on the locality exhibited by programs. Traditionally this l...
Dead blocks are handled inefficiently in multi-level cache hierarchies because the decision as to wh...
Dead blocks are handled inefficiently in the multi-level cache hierarchies of many-core architecture...
Last-level caches bridge the speed gap between processors and the off-chip memory hierarchy and redu...
Last-level caches (LLCs) bridge the processor/memory speed gap and reduce energy consumed per access...
Architects have adopted the shared memory model that implicitly manages cache coherence and cache ca...
Efficient cache hierarchy management is of a paramount importance when designing high performance pr...
The present disclosure generally relates to cache memory systems and/or techniques to identify dead ...
Cache memories currently treat all blocks as if they were equally important. This assumption of equa...
Multilevel caching is common in many storage config-urations, introducing new challenges to cache ma...
The design of a cache-coherent distributed shared memory (CCDSM) system is complex and prone to erro...
Memory hierarchies play an important role in microarchitectural design to bridge the performance gap...
As the technology continuous to shrink, power consumption appears to be the main design parameter. O...
This dissertation analyzes a way to improve cache performance via active management of a target cach...
Abstract—While many block replacement algorithms for buffer caches have been proposed to address the...
The performance of cache memories relies on the locality exhibited by programs. Traditionally this l...
Dead blocks are handled inefficiently in multi-level cache hierarchies because the decision as to wh...
Dead blocks are handled inefficiently in the multi-level cache hierarchies of many-core architecture...
Last-level caches bridge the speed gap between processors and the off-chip memory hierarchy and redu...
Last-level caches (LLCs) bridge the processor/memory speed gap and reduce energy consumed per access...
Architects have adopted the shared memory model that implicitly manages cache coherence and cache ca...
Efficient cache hierarchy management is of a paramount importance when designing high performance pr...
The present disclosure generally relates to cache memory systems and/or techniques to identify dead ...
Cache memories currently treat all blocks as if they were equally important. This assumption of equa...
Multilevel caching is common in many storage config-urations, introducing new challenges to cache ma...
The design of a cache-coherent distributed shared memory (CCDSM) system is complex and prone to erro...
Memory hierarchies play an important role in microarchitectural design to bridge the performance gap...
As the technology continuous to shrink, power consumption appears to be the main design parameter. O...
This dissertation analyzes a way to improve cache performance via active management of a target cach...
Abstract—While many block replacement algorithms for buffer caches have been proposed to address the...
The performance of cache memories relies on the locality exhibited by programs. Traditionally this l...