We develop real-time scheduling techniques for improving performance and energy for multiprogrammed workloads that scale non-uniformly with increasing thread counts. Multithreaded programs generally deliver higher throughput than single-threaded programs on chip multiprocessors, but performance gains from increasing threads decrease when there is contention for shared resources. We use analytic metrics to derive local search heuristics for creating efficient multiprogrammed, multithreaded workload schedules. Programs are allocated fewer cores than requested, and scheduled to space-share the CMP to improve global throughput. Our holistic approach attempts to co-schedule programs that complement each other with respect to shared resource cons...
Chip multi-processor (CMP) has become the most common processor in the current cluster and desktop c...
Microarchitectural techniques, such as superscalar instruction issue, Out-Of-Order instruction execu...
Future chip multiprocessors (CMPs) will be expected to deliver robust performance in the face of man...
Large, high frequency single-core chip designs are increasingly being replaced with larger chip mult...
Chip multicore processors (CMPs) have emerged as the dominant architecture choice for modern comput-...
This paper evaluates new techniques to improve performance and efficiency of Chip MultiProcessors (C...
Single-ISA heterogeneous multi-core processors trade-off power with performance; however, threads th...
Chip multicore processors (CMPs) have become the default architecture for modern desktops and server...
Emerging architecture designs include tens of processing cores on a single chip die; it is believed ...
The parallel nature of process execution on chip multiprocessors (CMPs) has considerably boosted lev...
In multicore systems, shared resources such as caches or the memory subsystem can lead to contention...
Abstract. On-chip resource sharing among sibling cores causes resource con-tention on Chip Multiproc...
Chip-level multiprocessors (CMP) have multiple processing cores (Cores) and generally have their cac...
The industry is rapidly moving towards the adoption of Chip Multi-Processors (CMPs) of Simultaneous ...
Abstract—One of the benefits of multiprogramming in con-ventional systems is to allow effective use ...
Chip multi-processor (CMP) has become the most common processor in the current cluster and desktop c...
Microarchitectural techniques, such as superscalar instruction issue, Out-Of-Order instruction execu...
Future chip multiprocessors (CMPs) will be expected to deliver robust performance in the face of man...
Large, high frequency single-core chip designs are increasingly being replaced with larger chip mult...
Chip multicore processors (CMPs) have emerged as the dominant architecture choice for modern comput-...
This paper evaluates new techniques to improve performance and efficiency of Chip MultiProcessors (C...
Single-ISA heterogeneous multi-core processors trade-off power with performance; however, threads th...
Chip multicore processors (CMPs) have become the default architecture for modern desktops and server...
Emerging architecture designs include tens of processing cores on a single chip die; it is believed ...
The parallel nature of process execution on chip multiprocessors (CMPs) has considerably boosted lev...
In multicore systems, shared resources such as caches or the memory subsystem can lead to contention...
Abstract. On-chip resource sharing among sibling cores causes resource con-tention on Chip Multiproc...
Chip-level multiprocessors (CMP) have multiple processing cores (Cores) and generally have their cac...
The industry is rapidly moving towards the adoption of Chip Multi-Processors (CMPs) of Simultaneous ...
Abstract—One of the benefits of multiprogramming in con-ventional systems is to allow effective use ...
Chip multi-processor (CMP) has become the most common processor in the current cluster and desktop c...
Microarchitectural techniques, such as superscalar instruction issue, Out-Of-Order instruction execu...
Future chip multiprocessors (CMPs) will be expected to deliver robust performance in the face of man...