Properties of Metal/High-k Oxide/Graphene Structures

The challenge of interpreting experimental data from capacitance versus voltage (C-V) measurements on metal/high-k oxide/graphene (MOG) structures is discussed. Theoretical expressions for the influence of interface states, bulk oxide traps, measurement frequency, temperature and puddles are derived and compared with experiments. The nature of oxide traps and their impact on C-V data is treated especially from the view of electron-lattice interaction at electron emission and capture and possible performance as border traps, resembling interface states. We find that characterization on detailed physical origins leading to effects on C-V data is a more complicated issue than the corresponding analysis of metal/oxide/semiconductor (MOS) structures