Add to ORKGAn improved state-space analysis of the CMOS static RAM cell is presented. Introducing the concept of the dividing line, the critical charge for heavy-ion-induced upset of memory cells can be calculated considering symmetrical as well as asymmetrical capacitive loads. From the critical charge, the upset-rate per bit-day for static RAMs can be estimated
The single event upset (SEU) imaging has been applied at the GSI heavy ion microprobe to determine t...
ventional way to analyze the robustness of an SRAM bit cell is to quantify its immunity to static no...
Abstract — Single-event upset effects from heavy ions were measured for Motorola silicon-on-insulato...
An improved state-space analysis of the CMOS static RAM cell is presented. Introducing the concept o...
The basic mechanisms of single-event upset are reviewed, including charge collection in silicon junc...
We have studied Single Event Effects in static and dynamic registers designed in a quarter micron CM...
We have studied single event effects in static and dynamic registers designed in a quarter micron CM...
A novel design technique is proposed for storage elements which are insensitive to radiation-induced...
Static random access memory cells (SRAM) are high-speed semiconductor memory that uses flip-flop to...
This paper presents the design of a static RAM cell in 65 nm CMOS technology. A good level of radiat...
A dedicated high-speed 18 Kbit static memory featuring synchronous mode, parity and dual port access...
A dedicated high-speed 18 Kbit static memory featuring synchronous mode, parity and dual port access...
As transistor sizes scale down to nanometres dimensions, CMOS circuits become more sensitive to radi...
Heavy charged particle induced soft errors in semiconductor memory devices have been a field failure...
Static random access memory (SRAM) is one the most sensitive devices to radiation. It may often exhi...
The single event upset (SEU) imaging has been applied at the GSI heavy ion microprobe to determine t...
ventional way to analyze the robustness of an SRAM bit cell is to quantify its immunity to static no...
Abstract — Single-event upset effects from heavy ions were measured for Motorola silicon-on-insulato...
An improved state-space analysis of the CMOS static RAM cell is presented. Introducing the concept o...
The basic mechanisms of single-event upset are reviewed, including charge collection in silicon junc...
We have studied Single Event Effects in static and dynamic registers designed in a quarter micron CM...
We have studied single event effects in static and dynamic registers designed in a quarter micron CM...
A novel design technique is proposed for storage elements which are insensitive to radiation-induced...
Static random access memory cells (SRAM) are high-speed semiconductor memory that uses flip-flop to...
This paper presents the design of a static RAM cell in 65 nm CMOS technology. A good level of radiat...
A dedicated high-speed 18 Kbit static memory featuring synchronous mode, parity and dual port access...
A dedicated high-speed 18 Kbit static memory featuring synchronous mode, parity and dual port access...
As transistor sizes scale down to nanometres dimensions, CMOS circuits become more sensitive to radi...
Heavy charged particle induced soft errors in semiconductor memory devices have been a field failure...
Static random access memory (SRAM) is one the most sensitive devices to radiation. It may often exhi...
The single event upset (SEU) imaging has been applied at the GSI heavy ion microprobe to determine t...
ventional way to analyze the robustness of an SRAM bit cell is to quantify its immunity to static no...
Abstract — Single-event upset effects from heavy ions were measured for Motorola silicon-on-insulato...