A proven approach to increase performance of general-purpose processors is to add hardware accelerators. In its basic configuration, the FlexCore processor has a limited set of datapath units. But thanks to a flexible datapath interconnect and a wide control word, the FlexCore datapath is explicitly designed to support integration of special units that, on demand, can accelerate certain data-intensive applications. We present the integration of a versatile accelerator for several Cyclic Redundancy Checking (CRC) keys. Furthermore, we investigate the accelerator\u27s impact on processor execution time and energy efficiency, using the PowerStone CRC benchmark. Our evaluation shows that the accelerated 65-nm 2.7-ns FlexCore datapath is, for ex...
Abstract — Error detection is important whenever there is a non-zero chance of data getting corrupte...
Abstract—A new hardware scheme for computing the transition and con-trol matrix of a parallel cyclic...
International audienceRecent trends of CMOS scaling and use of large last level caches (LLCs) have l...
Tailored to run domain-specific applications under very strict constraints on, for example, real-tim...
As a simple five-stage General-Purpose Processor (GPP), the baseline FlexCore processor has a limite...
We introduce FlexCore, the first exemplar of an architecture based on the FlexSoC framework. Compris...
Due to diversified demands of customers, embedded processor datapaths have been extended to accept m...
The design of an embedded processor is dependent on the application domain. Traditionally, design so...
The FlexCore processor is the resulting implementation of an exposed datapath approach conceptualize...
The comfort of our daily lives has come to rely on a vast number of embedded systems, such as mobile...
We introduce FlexCore, which is the first exemplar of a processor based on the FlexSoC processor par...
Cyclic redundancy check (CRC) algorithms are widely used for error detection in wireless communicati...
Cyclic redundancy check (CRC) is widely used for error detection. For optimal performances a method ...
Abstract—The FlexCore processor is the resulting implementation of an exposed datapath approach conc...
An algorithm for software or hardware implementation is presented, allowing fast computation of Cycl...
Abstract — Error detection is important whenever there is a non-zero chance of data getting corrupte...
Abstract—A new hardware scheme for computing the transition and con-trol matrix of a parallel cyclic...
International audienceRecent trends of CMOS scaling and use of large last level caches (LLCs) have l...
Tailored to run domain-specific applications under very strict constraints on, for example, real-tim...
As a simple five-stage General-Purpose Processor (GPP), the baseline FlexCore processor has a limite...
We introduce FlexCore, the first exemplar of an architecture based on the FlexSoC framework. Compris...
Due to diversified demands of customers, embedded processor datapaths have been extended to accept m...
The design of an embedded processor is dependent on the application domain. Traditionally, design so...
The FlexCore processor is the resulting implementation of an exposed datapath approach conceptualize...
The comfort of our daily lives has come to rely on a vast number of embedded systems, such as mobile...
We introduce FlexCore, which is the first exemplar of a processor based on the FlexSoC processor par...
Cyclic redundancy check (CRC) algorithms are widely used for error detection in wireless communicati...
Cyclic redundancy check (CRC) is widely used for error detection. For optimal performances a method ...
Abstract—The FlexCore processor is the resulting implementation of an exposed datapath approach conc...
An algorithm for software or hardware implementation is presented, allowing fast computation of Cycl...
Abstract — Error detection is important whenever there is a non-zero chance of data getting corrupte...
Abstract—A new hardware scheme for computing the transition and con-trol matrix of a parallel cyclic...
International audienceRecent trends of CMOS scaling and use of large last level caches (LLCs) have l...