This paper presents a 4:1 multiplexer fabricated in InP double heterojunction bipolar transistor (DHBT) technology. The multiplexer works up to 165 Gb/s at a supply voltage of -3.2 V consuming 1.6 W. It is a half-rate multiplexer using a multi-phase clock architecture. The main design challenge was to ensure correct timing between clock and data signals. \ua9 2006 IEEE
In this paper, we report a manufacturable InP DHBT technology, suitable for medium scale mixed-signa...
In this paper, a 100 Gbit/s fully integrated clock and data recovery (CDR) circuit with 1:2 demultip...
In this paper, we report a manufacturable InP DHBT technology, suitable for medium scale mixed-signa...
It is now clear that 112-Gb/s data rate is the next step in the network evolution (100-Gb/s Ethernet...
International audienceWe report on an Indium Phosphide (InP) double heterojunction bipolar transisto...
Key components and architecture options are being actively investigated to realize next generation t...
An ultra-high speed 1bit full adder based on indium phosphide (InP) double heterojunction bipolar tr...
We report on design and test of state-of-the-art building blocks for a 100 Gb/s demonstrator system:...
In this work, up to 80 Gbit/s monolithically integrated clock and data recovery (CDR) circuits with ...
International audienceIn this Letter, the authors report on the design, optimisation and electrical ...
This letter reports the potential of an InP-based double-heterojunction bipolar transistor (DHBT) us...
In this paper, we report the achieved performance of devices and integrated circuits (ICs) using a m...
We report on the development of a double heterojunction bipolar transistor (DHBT) technology on InP ...
A InP/GaAsSb/InP double-heterojunction bipolar transistor (DHBT) structure has been defined, realize...
We report the performances of a 0.7-μm InP/GaInAs DHBT developed in III-V Lab demonstrating both f T...
In this paper, we report a manufacturable InP DHBT technology, suitable for medium scale mixed-signa...
In this paper, a 100 Gbit/s fully integrated clock and data recovery (CDR) circuit with 1:2 demultip...
In this paper, we report a manufacturable InP DHBT technology, suitable for medium scale mixed-signa...
It is now clear that 112-Gb/s data rate is the next step in the network evolution (100-Gb/s Ethernet...
International audienceWe report on an Indium Phosphide (InP) double heterojunction bipolar transisto...
Key components and architecture options are being actively investigated to realize next generation t...
An ultra-high speed 1bit full adder based on indium phosphide (InP) double heterojunction bipolar tr...
We report on design and test of state-of-the-art building blocks for a 100 Gb/s demonstrator system:...
In this work, up to 80 Gbit/s monolithically integrated clock and data recovery (CDR) circuits with ...
International audienceIn this Letter, the authors report on the design, optimisation and electrical ...
This letter reports the potential of an InP-based double-heterojunction bipolar transistor (DHBT) us...
In this paper, we report the achieved performance of devices and integrated circuits (ICs) using a m...
We report on the development of a double heterojunction bipolar transistor (DHBT) technology on InP ...
A InP/GaAsSb/InP double-heterojunction bipolar transistor (DHBT) structure has been defined, realize...
We report the performances of a 0.7-μm InP/GaInAs DHBT developed in III-V Lab demonstrating both f T...
In this paper, we report a manufacturable InP DHBT technology, suitable for medium scale mixed-signa...
In this paper, a 100 Gbit/s fully integrated clock and data recovery (CDR) circuit with 1:2 demultip...
In this paper, we report a manufacturable InP DHBT technology, suitable for medium scale mixed-signa...