This thesis concludes work conducted on exploring the usage of parallel and reconfigurableprocessor architectures in industrial high-performance embedded systems. This kind ofsystems has by tradition been built using a mix of digital signal processors and custommade hardware. Digital signal processors provide full functional flexibility, but at the costof lower performance. Custom made hardware can be optimized for specific functions forhigh performance, but at the cost of inflexibility and high development costs. A desire is tocombine flexibility and performance using commercial hardware, without trading too muchof performance for flexibility.Parallel and reconfigurable architectures provide a flexible computing space constitutingprocessin...
This paper presents the design and use of reconfigurable stream processors for the physical layer pr...
Digital data streams all have a common structure but they differ in small details. Dedicated hardwar...
This paper proposes a processor architecture for DR-SPE,a dynamic reconfigurable stream processing e...
This paper presents a configurable framework to be used for rapid prototyping of stream based langua...
Emerging applications such as high definition television (HDTV), streaming video, image processing i...
PhD ThesisEmerging applications such as high definition television (HDTV), streaming video, image pr...
Research Focus To be able to handle the rapidly increasing programming complexity of multicore proce...
In this paper we focus on algorithms and reconfigurable multi-core architectures for streaming digit...
This thesis is concerned with the specification, compilation and corresponding temporal analysis of ...
Tech ReportThis paper presents the design and use of reconfigurable stream processors for the physic...
A modern way of processing information is to do it in parallel. This Master Thesis conducts a case s...
Given the ubiquity of multicore processors, there is an acute need to enable the development of scal...
Stream applications are often limited in their performance by their underlying communication system....
This presentation will focus on algorithms and reconfigurable tiled architectures for streaming DSP ...
This thesis is concerned with the specification, compilation and corresponding temporal analysis of ...
This paper presents the design and use of reconfigurable stream processors for the physical layer pr...
Digital data streams all have a common structure but they differ in small details. Dedicated hardwar...
This paper proposes a processor architecture for DR-SPE,a dynamic reconfigurable stream processing e...
This paper presents a configurable framework to be used for rapid prototyping of stream based langua...
Emerging applications such as high definition television (HDTV), streaming video, image processing i...
PhD ThesisEmerging applications such as high definition television (HDTV), streaming video, image pr...
Research Focus To be able to handle the rapidly increasing programming complexity of multicore proce...
In this paper we focus on algorithms and reconfigurable multi-core architectures for streaming digit...
This thesis is concerned with the specification, compilation and corresponding temporal analysis of ...
Tech ReportThis paper presents the design and use of reconfigurable stream processors for the physic...
A modern way of processing information is to do it in parallel. This Master Thesis conducts a case s...
Given the ubiquity of multicore processors, there is an acute need to enable the development of scal...
Stream applications are often limited in their performance by their underlying communication system....
This presentation will focus on algorithms and reconfigurable tiled architectures for streaming DSP ...
This thesis is concerned with the specification, compilation and corresponding temporal analysis of ...
This paper presents the design and use of reconfigurable stream processors for the physical layer pr...
Digital data streams all have a common structure but they differ in small details. Dedicated hardwar...
This paper proposes a processor architecture for DR-SPE,a dynamic reconfigurable stream processing e...