We introduce FlexCore, which is the first exemplar of a processor based on the FlexSoC processor paradigm. TheFlexCore utilizes an exposed datapath for increased performance. Microbenchmarks yield a performance boost of a factor of two over a traditional five-stage pipeline with the same functional units as the FlexCore.We describe our approach to compiling for the FlexCore.A flexible interconnect allows the FlexCore datapath to bedynamically reconfigured as a consequence of code generation. Additionally, specialized functional units may be introduced and utilized within the same architecture and compilation framework. The exposed datapath requires a wide control word. The conducted evaluation of two micro benchmarks confirms that this incr...
Designing a processor is a complex task that uses multiple and varied tools. The complete developmen...
International audienceThis paper introduces the FlexTiles platform, which consist of a manycore arch...
A popular way to exploit high level programming languages in FPGA designs is to use a soft-core with...
We introduce FlexCore, the first exemplar of an architecture based on the FlexSoC framework. Compris...
The FlexCore processor is the resulting implementation of an exposed datapath approach conceptualize...
Abstract—The FlexCore processor is the resulting implementation of an exposed datapath approach conc...
Fine-grained control through the use of a wide control word can lead to high instruction-level paral...
The design of an embedded processor is dependent on the application domain. Traditionally, design so...
As a simple five-stage General-Purpose Processor (GPP), the baseline FlexCore processor has a limite...
The FlexSoC project aims at developing a design framework that makes it possible to combine the comp...
The comfort of our daily lives has come to rely on a vast number of embedded systems, such as mobile...
A proven approach to increase performance of general-purpose processors is to add hardware accelerat...
The goal of this project is to design an instruction decoder for the FlexCore processor based on an ...
In this paper, we present a new architectural concept for network processors called FlexPath NP. The...
Due to diversified demands of customers, embedded processor datapaths have been extended to accept m...
Designing a processor is a complex task that uses multiple and varied tools. The complete developmen...
International audienceThis paper introduces the FlexTiles platform, which consist of a manycore arch...
A popular way to exploit high level programming languages in FPGA designs is to use a soft-core with...
We introduce FlexCore, the first exemplar of an architecture based on the FlexSoC framework. Compris...
The FlexCore processor is the resulting implementation of an exposed datapath approach conceptualize...
Abstract—The FlexCore processor is the resulting implementation of an exposed datapath approach conc...
Fine-grained control through the use of a wide control word can lead to high instruction-level paral...
The design of an embedded processor is dependent on the application domain. Traditionally, design so...
As a simple five-stage General-Purpose Processor (GPP), the baseline FlexCore processor has a limite...
The FlexSoC project aims at developing a design framework that makes it possible to combine the comp...
The comfort of our daily lives has come to rely on a vast number of embedded systems, such as mobile...
A proven approach to increase performance of general-purpose processors is to add hardware accelerat...
The goal of this project is to design an instruction decoder for the FlexCore processor based on an ...
In this paper, we present a new architectural concept for network processors called FlexPath NP. The...
Due to diversified demands of customers, embedded processor datapaths have been extended to accept m...
Designing a processor is a complex task that uses multiple and varied tools. The complete developmen...
International audienceThis paper introduces the FlexTiles platform, which consist of a manycore arch...
A popular way to exploit high level programming languages in FPGA designs is to use a soft-core with...