The early assessment of the fault tolerance mechanisms is an essential task in the design of dependable computing systems. Simulation languages offer the necessary support to carry out such a task. Due to its wide spectrum of application and hierarchical features, VHDL is a powerful simulation language. This chapter summarizes the main results of a pioneering effort aimed at developing and experimenting supporting tools for fault injection into VHDL models. The chapter first identifies the possible means to inject faults into a VHDL model. Then, we describe two prototype tools that were developed using each of the main injection strategies previously identified. Finally, some general insights and perspectives are briefly discussed
AbstractThe state of the art in hardware design is the use of hardware description languages such as...
This paper presents an analysis process targeted for the verification of fault secure systems during...
The state of the art in integrated circuit design is the use of special hardware description languag...
This thesis deals with the design and validation of low-cost error detecting mechanisms that can be ...
This thesis deals with the design and validation of low-cost error detecting mechanisms that can be ...
INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 0923-8174The probability of transi...
Simulation-based Fault Injection in VHDL descriptions is increasingly common due to the popularity o...
A technique is described for the automatic insertion of fault models into VHDL gate models, using sh...
International audienceThe probability of transient faults increases with the evolution of technologi...
This paper proposes a high level technique to inject transient faults in processor-like circuits, an...
ISBN: 0769507190Analyzing at an early stage of the design the potential faulty behaviors of a circui...
International audienceThe tools that are used to inject faults in FPGA based implementations are gen...
For high quality VLSI products, exhibiting very low escape rates, defect-oriented testing becomes ma...
As CMOS technology scales to the nanometer range, designers have to deal with a growing number and v...
Fault injection in VHDL descriptions has become an efficient solution to analyze at an early stage o...
AbstractThe state of the art in hardware design is the use of hardware description languages such as...
This paper presents an analysis process targeted for the verification of fault secure systems during...
The state of the art in integrated circuit design is the use of special hardware description languag...
This thesis deals with the design and validation of low-cost error detecting mechanisms that can be ...
This thesis deals with the design and validation of low-cost error detecting mechanisms that can be ...
INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 0923-8174The probability of transi...
Simulation-based Fault Injection in VHDL descriptions is increasingly common due to the popularity o...
A technique is described for the automatic insertion of fault models into VHDL gate models, using sh...
International audienceThe probability of transient faults increases with the evolution of technologi...
This paper proposes a high level technique to inject transient faults in processor-like circuits, an...
ISBN: 0769507190Analyzing at an early stage of the design the potential faulty behaviors of a circui...
International audienceThe tools that are used to inject faults in FPGA based implementations are gen...
For high quality VLSI products, exhibiting very low escape rates, defect-oriented testing becomes ma...
As CMOS technology scales to the nanometer range, designers have to deal with a growing number and v...
Fault injection in VHDL descriptions has become an efficient solution to analyze at an early stage o...
AbstractThe state of the art in hardware design is the use of hardware description languages such as...
This paper presents an analysis process targeted for the verification of fault secure systems during...
The state of the art in integrated circuit design is the use of special hardware description languag...