We propose a modeling methodology, including power models, thatcaptures the dependence of leakage power on temperature and supply voltagevariations for accurate architectural-level power estimation of physically partitionedand un-partitioned SRAMarrays. A simulation -based modeling approachis used for temperature-aware leakage power estimation, while a physically-basedanalytical approach is used for modeling the leakage dependence of memory cellson supply voltage. By using the new power models, it is, for example, possibleto preserve our previously reported power estimation accuracy of 96% also in thepresence of temperature and voltage variations
Increasing variability during manufacturing and during runtime are projected for future generation m...
Increasing variability during manufacturing and during runtime are projected for future generation m...
Suppressing the leakage current in memories is critical in low-power design. By reducing the standby...
We propose a modeling methodology, including power models, that captures the dependence of leakage p...
We propose a methodology and power models for an accuratehigh-level power estimation of physically p...
Following Moore’s Law, technology scaling will continue providing integration capacityof billions of...
Abstract — The need to perform power analysis in the early stages of the design process has become c...
[[abstract]]In this paper, we present an automatic leakage power modeling method for standard cell l...
Abstract — This paper presents two fast and accurate methods to estimate the lower bound of supply v...
In this paper, we present power models with clock and tem-perature scaling, and develop the first of...
Abstract—It has been the conventional assumption that, due to the superlinear dependence of leakage ...
The dominance of leakage currents in circuit design has been impelled by steady downscaling of MOSFE...
Static power dissipation due to leakage current in transistors constitutes an increasing fraction of...
International audienceModern systems-on-a-chip are equipped with power architectures, allowing to co...
Abstract—This paper presents a novel framework for accurate estimation of key statistical parameters...
Increasing variability during manufacturing and during runtime are projected for future generation m...
Increasing variability during manufacturing and during runtime are projected for future generation m...
Suppressing the leakage current in memories is critical in low-power design. By reducing the standby...
We propose a modeling methodology, including power models, that captures the dependence of leakage p...
We propose a methodology and power models for an accuratehigh-level power estimation of physically p...
Following Moore’s Law, technology scaling will continue providing integration capacityof billions of...
Abstract — The need to perform power analysis in the early stages of the design process has become c...
[[abstract]]In this paper, we present an automatic leakage power modeling method for standard cell l...
Abstract — This paper presents two fast and accurate methods to estimate the lower bound of supply v...
In this paper, we present power models with clock and tem-perature scaling, and develop the first of...
Abstract—It has been the conventional assumption that, due to the superlinear dependence of leakage ...
The dominance of leakage currents in circuit design has been impelled by steady downscaling of MOSFE...
Static power dissipation due to leakage current in transistors constitutes an increasing fraction of...
International audienceModern systems-on-a-chip are equipped with power architectures, allowing to co...
Abstract—This paper presents a novel framework for accurate estimation of key statistical parameters...
Increasing variability during manufacturing and during runtime are projected for future generation m...
Increasing variability during manufacturing and during runtime are projected for future generation m...
Suppressing the leakage current in memories is critical in low-power design. By reducing the standby...