Add to ORKGInternational audienceIn this paper, using extensive TCAD simulations and measurement results, we analyze the basic mechanisms involved during an ESD stress in a self-biased NPN bipolar transistor used as an ESD protection. From the deep understanding of these mechanisms, we define design guidelines to achieve a very high ESD robustness (=10kV) in this type of device. These guidelines are validated on several CMOS technologies
International audienceThis paper proposes a 1D-analytical description of the injection ratio of a se...
ESD protection capability of SOI CMOS output buffers has been studied with Human Body Model (HBM) st...
BCD electrostatic discharge (ESD) protection npn devices with and without a sinker are analyzed expe...
International audienceIn this paper, using extensive TCAD simulations and measurement results, we an...
International audienceImproving the ESD robustness of integrated protection structures to cope with ...
We present the results of extensive characterization of fully isolated SOI NPN bipolar protection de...
The research work presented in this thesis is aimed at improving the performance of electrostatic di...
Abstract—This paper presents a detailed investigation of the degradation of electrostatic discharge ...
The aim of this dissertation was to develop protections structures against electrostatic discharges ...
9 pagesInternational audienceA thorough analysis of the physical mechanisms involved in a Vertical G...
ESD protection devices comprising polysilicon resistor, Vcc and Vss connected diodes with different ...
sites and three latchup paths clarified through careful and intensive FIB failure analysis, while th...
Abstract—One method to enhance electrostatic discharge (ESD) robustness of the on-chip ESD protectio...
International audienceEfficient energy management become more and more crucial with increasing energ...
This paper demonstrates a fully-silicided ESD protection device design in sub-100nm integrated circu...
International audienceThis paper proposes a 1D-analytical description of the injection ratio of a se...
ESD protection capability of SOI CMOS output buffers has been studied with Human Body Model (HBM) st...
BCD electrostatic discharge (ESD) protection npn devices with and without a sinker are analyzed expe...
International audienceIn this paper, using extensive TCAD simulations and measurement results, we an...
International audienceImproving the ESD robustness of integrated protection structures to cope with ...
We present the results of extensive characterization of fully isolated SOI NPN bipolar protection de...
The research work presented in this thesis is aimed at improving the performance of electrostatic di...
Abstract—This paper presents a detailed investigation of the degradation of electrostatic discharge ...
The aim of this dissertation was to develop protections structures against electrostatic discharges ...
9 pagesInternational audienceA thorough analysis of the physical mechanisms involved in a Vertical G...
ESD protection devices comprising polysilicon resistor, Vcc and Vss connected diodes with different ...
sites and three latchup paths clarified through careful and intensive FIB failure analysis, while th...
Abstract—One method to enhance electrostatic discharge (ESD) robustness of the on-chip ESD protectio...
International audienceEfficient energy management become more and more crucial with increasing energ...
This paper demonstrates a fully-silicided ESD protection device design in sub-100nm integrated circu...
International audienceThis paper proposes a 1D-analytical description of the injection ratio of a se...
ESD protection capability of SOI CMOS output buffers has been studied with Human Body Model (HBM) st...
BCD electrostatic discharge (ESD) protection npn devices with and without a sinker are analyzed expe...