Optimized power combining technique to design a 20dB gain, 13.5dBm OCP1dB 60GHz Power Amplifier using 65nm CMOS Technology

International audienceMillimeter-wave Distributed Active Transformer (DAT), baluns and zero degree 1−4 splitter have been optimized to design a 60 GHz parallel Power Amplifier (PA). The implementation is based on a thin digital 7 metal layers (1P7M) Back End of Line (BEOL) and Low Power (LP) transistors in 65 nm CMOS technology from STMicroelectronics. A lumped model based analysis is presented to compare pure voltage and mixed voltage and current combining techniques. Simulated and measured results are reported. At 61 GHz, the PA achieves a peak power gain of 20 dB with a 13.5 dBm 1dB-output compression point (OCP1dB), 15.6 dBm output power and a Power Added Efficiency (PAE) of 6.6% from a 1.2 V supply. To the author's knowledge, these results represent the highest linear output power and gain performances among PAs using the same technolog