Optimization of a MOS–IGBT–SCR ESD protection component in smart power SOI technology

International audienceA MOS-IGBT-SCR component that was proposed in a previous paper to increase the device robustness and the cost of ESD protection circuit is optimized in this paper. In order to improve its latch up immunity, several variations of geometrical parameters that have been simulated using TCAD Sentaurus Device in another previous paper have been implemented and compared in this paper. The drift area, the form factor, and the proportion of P + sections inserted into the drain are the main parameters, which have a significant impact on the latch up immunity. TLP characterization, and curve tracer measurements have been carried out to evaluate the proposed solution. Holding current increases up to 70 mA and holding voltage up to 10 V. 1 Introduction The electrostatic discharge (ESD) has always been one of the highest reliability concerns in the integrated (IC) manufacturing industry. With the continuous miniaturization process, the integrated circuits become more and more vulnerable to ESD. The miniaturization of the ESD protection blocks is one of the greatest challenges of smart power technologies. Silicon On Insulator (SOI) technologies allow extending the operational temperature range while providing the necessary isolation between components with a reduced silicon area. SOI technology is becoming more and more attractive to manage very high voltage blocks, to reduce parasitic NPN effect and to increase Integrated Circuit (IC) speed as well as for applications operating at high temperature [1], [2]. Electro Static Discharge (ESD) protections occupy a significant silicon IC area. Using a LDMOS as main ESD protection component is not optimal due to its high on-resistance, but it could be the only solution for some technologies. In a previous work, we proposed a new ESD component (MOS-IGBT-SCR) and improved it in order to increase ESD performance and improve the latch up immunity [3] [4]. ESD performance was excellent but margin to prevent latch up was not satisfying. In this paper, an optimized version of this structure is discussed and experimentally validated. As the technological parameters of the used technology (TFSMART1: SOI smart power technology) cannot be changed, we explored various layout-design solutions such as the device topology or the architecture. 2 Structure description and preview solutio