High-Density 3-D Capacitors for Power Systems On-Chip: Evaluation of a Technology Based on Silicon Submicrometer Pore Arrays Formed by Electrochemical Etching

International audienceThis paper presents the state of the art technologies currently used to produce high density integrated capacitors for power systems on-chip applications. The use of high-k dielectrics and 3D patterning of silicon for reaching high specific capacitance is reviewed. Integrating capacitors monolithically on the active chip or in package of power systems is discussed and solutions are proposed for minimising series resistance and achieving a high level of integration. A technology based on nanolithography and silicon electrochemical etching is then detailed. It is shown that capacitance densities of up to 700 nF/mm² can be obtained with a submicrometer pores array in a relatively limited thickness. The advantages and disadvantages of further decreasing the pore size to nanosize pores (below 100 nm) are discussed