Hardware accelerator for high performance computer based video coding algorithm

Porast popularnosti internetskih video usluga dovodi do značajnog porasta udjela video prometa u Internet prometu. Jedan od načina za povećanje performanci sustava za rad s video uslugama je razvoj sklopa za ubrzanje. U ovom radu računalo je povezano s FPGA sklopom korištenjem PCI Express sabirnice. Analiziran je HEVC koder. U programabilnoj logici ostvaren je sklop za izvođenje dijela HEVC kodera. Razvijeno je više verzija sklopa i ispitane su različite arhitekture sustava. Kodiran je video pomoću ostvarenog FPGA sklopa i napravljena je usporedba vremena izvođenja.Rise in popularity of the internet video services brings us to rise in the internet video traffic. One possibility for enhancing performances of systems for running video services is developing an accelerator. In this thesis personal computer is connected with FPGA logic using the PCI Express bus. HEVC encoder is analyzed. Hardware accelerator for part of the HEVC encoder algorithm is implemented. Multiple versions of accelerator are developed and different architectures are tested. Sample video is encoded using implemented FPGA accelerator and running time comparison is made