Implementation of machine learning on field-programmable gate array

Rad obrađuje implementaciju konkretnog algoritma strojnog učenja na programirljivom polju logičkih blokova tj. u obliku digitalnog sklopa. Počevši od grubog opisa algoritma te implementacije u višim programskim jezicima, postepeno se razrađuju poteškoće i prilagodbe što konačno rezultira gotovim sklopom upisanom u jeziku za opis sklopovlja Verilog. Također, obrađuje se kratak uvod u područje strojnog učenja i klasifikacije te se odabire prigodni algoritam. Konačno se relativno detaljno opisuje gotovi sklop te princip rada pojedinih komponenti.The subject of this paper covers the implementation of a particular machine learning algorithm on a field-programmable gate array in the form of a digital circuit. With the abstract, high-level description as a base, the algorithm is gradually modified to fit the environment resulting in a complete digital system written in the hardware description language Verilog. A basic introduction to the field of machine learning and classification is covered along with the process of choosing an appropriate algorithm is also. The final solution presents a complete digital system, describing the core principals and components