Recording and playback of video signals with support for multiple cameras based on FPGAs

Zadatak ovog diplomskog rada je napraviti FPGA dizajn koji omogućava AMV Grabber ploči primanje i zapisivanje podataka s kamera, te slanje već snimljenog video sadržaja na izlazne portove. AMV Grabber ploča ima ulogu produžetka ADAS (engl. Advanced Driver Assistance System) uređaja, jer AMV Grabber omogućava lakši razvoj i testiranje ADAS algoritama. Dizajniranje je odrađeno u Xilinx®-ovom okruženju Vivado®, te su korišteni službeni IP blokovi koje regulira Xilinx®. Rješenje je razdvojeno na dva dijela, putanja snimanja i putanja reprodukcije iz razloga što nije bilo moguće putanju reprodukcije implementirati u kompletan projekt. Omogućeno je snimanje do devet kamera, iako hardverska ograničenja nisu dozvoljavala dovoljan protok podataka, usko grlo se pojavilo pri zapisivanju podataka na tvrdi disk. Putanja reprodukcije je razvijena zasebno i potvrda njene funkcionalnosti zahtijevala je pozamašna testiranja. Ispostavilo se da je slanje moguće, uz mali gubitak pet početnih okvira koje je nemoguće sačuvati jer su potrebni za sinkronizaciju blokova u dizajnu reprodukcije.The purpose of this master thesis is to create an FPGA design, which allows capturing data from cameras, and reproduction of already captured data to the output ports on AMV Grabber device. AMV Grabber device acts as an extension of ADAS (Advanced Driver Assistance Systems) which allows easier development and testing of ADAS algorithms. The design has been made in Vivavo® design suite by Xilinx®. For the purposes of the design official IPs have been used. Developed design is separated into two parts, input path, and output path, because output path was not possible to implement into the complete project. Input path is able to record with up to nine cameras, even though only theoretically. Actual capabilities were the recording with five cameras because there happened to be a data flow bottle neck when writing on the SSD drive, and no AMV Grabber device had all nine input ports functional. Output path was developed on its own, so the verification of requested behavior was extensive. The final result was successful reproduction of test data with first five frame loss, due to synchronization process of the IPs used in the output design