High-speed camera serial interface verification

This thesis focuses on the D-PHY interface verification defined by the international MIPI alliance. The interface is a commonly used standard in the mobile camera and display interface and most of the component suppliers directly support that standard. The current standard revision is the third approved version. When the first standard version supported 1 Gbps per lane, the current version supports lane-speed up to 2.5 Gbps. The increase in bandwidth has brought new needs for the signal integrity verification. During the past years, the camera signal integrity has not been a critical design parameter. Nowadays, the interface performance is often close to its electrophysical limits and many design parameters need to be considered during the system design phase. The purpose of this thesis is to create a reliable verification environment for the D-PHY camera interface verification. The target for quality is to build a reference level measurement environment. The system will replace manual measurements which take a lot of resources. The system will be used in verification, but as important as the verification is to understand better the current and incoming challenges and practical limits in system design