Superimposed In-circuit fault mitigation for dynamically reconfigurable FPGAs

Reassuring fault tolerance in computing systems is the most important problem for mission critical space com- ponents. With the rise in interest of commercial SRAM-based FPGAs, it is crucial to provide runtime reconfigurable recovery from a failure. In this paper we propose a superimposed virtual coarse-grained reconfigurable architecture, embedded an on- demand three level fault-mitigation technique tailored for FPGA overlays. The proposed method performs run-time recovery via Microscrubbing. This approach can achieve up to 3× faster run- time recovery with 10.2× less resources in FPGA devices, by providing integrated layers of fault mitigation