Null Convention Logic (NCL) is a robust asynchronous technique that poses new challenges to test and testability strategies due to the lack of a clock signal and the state-holding behavior of the NCL gates. The lack of deterministic timing in NCL complicates the management of test timing, and stuck-at faults on gate internal feedback (GIF) of the NCL gates exhibit a totally different effect compared to that of stuck-at faults on the gate inputs. Stuck-at faults on gate internal feedback of NCL gates do not always cause an incorrect output and therefore are considered hard-to-detect or undetectable by automatic test pattern generation (ATPG) algorithms. Such faults could leave the primary outputs of the circuit completely unaffected or somet...
Abstract: Testability analysis of basic and complex logic gates employing complementary pass transis...
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within t...
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within t...
Due to the absence of a global clock and the presence of more state holding elements that synchroniz...
Due to the absence of a global clock and presence of more state holding elements that synchronize th...
Conventional automatic test pattern generation (ATPG) algorithms fail when applied to asynchronous N...
In the past two decades, the IC Design industry has set what one might refer to as milestones in the...
Design for testability (DFT) refers to a new hardware that reduces check generation quality and chec...
NULL Convention Logic (NCL) is a Quasi-Delay Insensitive (QDI) asynchronous design paradigm that aim...
Testing of an electronic chip is an important step in the design process, as it can detect faults an...
Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of...
This dissertation is concerned with testing of asynchronous circuits. Asynchronous circuits are attr...
Abstract — Interest in asynchronous circuits has increased in the VLSI research community due the gr...
Self-timed properly judgment layout strategies are advanced the usage of Threshold Combinational Red...
Abstract—Interest in asynchronous circuits has increased in the VLSI research community due to the g...
Abstract: Testability analysis of basic and complex logic gates employing complementary pass transis...
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within t...
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within t...
Due to the absence of a global clock and the presence of more state holding elements that synchroniz...
Due to the absence of a global clock and presence of more state holding elements that synchronize th...
Conventional automatic test pattern generation (ATPG) algorithms fail when applied to asynchronous N...
In the past two decades, the IC Design industry has set what one might refer to as milestones in the...
Design for testability (DFT) refers to a new hardware that reduces check generation quality and chec...
NULL Convention Logic (NCL) is a Quasi-Delay Insensitive (QDI) asynchronous design paradigm that aim...
Testing of an electronic chip is an important step in the design process, as it can detect faults an...
Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of...
This dissertation is concerned with testing of asynchronous circuits. Asynchronous circuits are attr...
Abstract — Interest in asynchronous circuits has increased in the VLSI research community due the gr...
Self-timed properly judgment layout strategies are advanced the usage of Threshold Combinational Red...
Abstract—Interest in asynchronous circuits has increased in the VLSI research community due to the g...
Abstract: Testability analysis of basic and complex logic gates employing complementary pass transis...
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within t...
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within t...