Untersuchung des elektronischen Transports an 28nm MOSFETs und an Schottky-Barrieren FETs aus Silizium-Nanodrähten

As modern microelectronics advances, enormous challenges have to be overcome in order to further increase device performance, enabling highspeed and ultra-low-power applications. With progressive scaling of Silicon MOSFETs, charge carrier mobility has dropped significantly and became a critical device parameter over the last decade. Present technology nodes make use of strain engineering to partially recover this mobility loss. Even though carrier mobility is a crucial parameter for present technology nodes, it cannot be determined accurately by methods typically available in industrial environments. A major objective of this work is to study the magnetoresistance mobility μMR of strained VLSI devices based on a 28 nm ground rule. This technique allows for a more direct access to charge carrier mobility, compared to conventional current/ voltage and capacitance/ voltage mobility derivation methods like the effective mobility μeff, in which series resistance, inversion charge density and effective channel length are necessary to extract the mobility values of the short channel devices. Aside from providing an anchor for accurate μeff measurements in linear operation conditions, μMR opens the possibility to investigate the saturation region of the device, which cannot be accessed by μeff. Electron and hole mobility of nFET and pFET devices with various gate lengths are studied from linear to saturation region. In addition, the interplay between mobility enhancement due to strain improvement, and mobility degradation due to short channel effects with decreasing channel length is analyzed. As a concept device for future nanoelectronic building blocks, silicon nanowire Schottky field-effect transistors are investigated in the second part of this work. These devices exhibit an ambipolar behaviour, which gives the opportunity to measure both electron and hole transport on a single device. The temperature dependence of the source/drain current for specific gate and drain voltages is analyzed within the framework of voltage dependent effective barrier heights.:1. Einleitung 2. Theoretische Grundlagen 3. Charakterisierungsmethoden 4. Messaufbau 5. Ergebnisse der Untersuchungen an MOSFETs 6. Ergebnisse der Untersuchungen an SiNW Transistoren 7. Zusammenfassung Anhang Danksagunge