Hierarchical Model Partitioning for Parallel VLSI-Simulation Using Evolutionary Algorithms improved bei superpositions of partitions

Parallelization of VLSI-simulation exploiting model-inherent parallelism is a promising way to accelerate verification processes for whole processor designs. Thereby partitioning of hardware models influences the effciency of following parallel simulations essentially. Based on a formal model of Parallel Cycle Simulation we introduce partition valuation combining communication and load balancing aspects. We choose a 2-level hierarchical partitioning scheme providing a framework for a mixture of experts strategy. Considering a complete model of a PowerPC 604 processor, we demonstrate that Evolutionary Algorithms can be applied successfully to our model partitioning problem on the second hierarchy level, supposing a reduced problem complexity after fast pre-partitioning on the first level. For the first time, we apply superpositions during execution of Evolutionary Algorithms, resulting in a faster decreasing fitness function and an acceleration of population handling