Hyperreconfigurable architectures adapt their reconfiguration abilities during run time in order to achieve fast dynamic reconfiguration. Models for such architectures have been proposed that change their ability for reconfiguration during hyperreconfiguration steps and in ordinary reconfiguration steps reconfigure the actual contexts for a computation within the limits that have been set by the last hyperreconfiguration step. In this paper we study algorithmic aspects of how to optimally decide what hyperreconfiguration steps should be done during a computation in order to minimize the total time necessary for hyperreconfiguration and ordinary reconfiguration. It is shown that the general problem is NP-hard but fast polynomial time algorit...
The occurrence of faults in multicomputers with hundreds or thousands of nodes is a likely event tha...
Many reconfigurable architectures offer partial dynamic configura-bility, but current system-level t...
In this paper we study multi-level dynamically reconfigurable architectures. These are extensions of...
Hyperreconfigurable architectures adapt their reconfiguration abilities during run time in order to ...
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or st...
Hyperreconfigurable architectures can adapt their reconfiguration abilities during run time and have...
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or st...
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or st...
Abstract: Hyperreconfigurable architectures can change their reconfiguration capa-bilities dynamical...
Abstract—The architecture and use of caches for two-level reconfigurable hardware is studied in this...
In this paper we consider the problem of reconfiguring processor arrays subject to computational loa...
Configurable computing has recently gained much attention with the promise of delivering an order of...
Parallel processing techniques are increasingly found in reconfigurable computing, especially in dig...
Configurable computing has recently gained much attention with the promise of delivering an order of...
Several parallel parallel processing systems exist that can be partitioned and/or can operate in mul...
The occurrence of faults in multicomputers with hundreds or thousands of nodes is a likely event tha...
Many reconfigurable architectures offer partial dynamic configura-bility, but current system-level t...
In this paper we study multi-level dynamically reconfigurable architectures. These are extensions of...
Hyperreconfigurable architectures adapt their reconfiguration abilities during run time in order to ...
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or st...
Hyperreconfigurable architectures can adapt their reconfiguration abilities during run time and have...
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or st...
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or st...
Abstract: Hyperreconfigurable architectures can change their reconfiguration capa-bilities dynamical...
Abstract—The architecture and use of caches for two-level reconfigurable hardware is studied in this...
In this paper we consider the problem of reconfiguring processor arrays subject to computational loa...
Configurable computing has recently gained much attention with the promise of delivering an order of...
Parallel processing techniques are increasingly found in reconfigurable computing, especially in dig...
Configurable computing has recently gained much attention with the promise of delivering an order of...
Several parallel parallel processing systems exist that can be partitioned and/or can operate in mul...
The occurrence of faults in multicomputers with hundreds or thousands of nodes is a likely event tha...
Many reconfigurable architectures offer partial dynamic configura-bility, but current system-level t...
In this paper we study multi-level dynamically reconfigurable architectures. These are extensions of...