Test response compaction for built-in self testing.

Built-in self testing (BIST) offers an attractive solution to the problem of testing complex VLSI circuits. An important aspect of BIST is response compaction in which the test response is compressed in both the space and time dimensions to a compact signature. A fundamental problem with compaction is aliasing, which occurs when a faulty response maps to the fault-free signature. This thesis develops a formal theory of response compaction and presents several techniques for aliasing-free compaction of test responses. Unlike most previous techniques that assume pseudorandom tests, our methods are also applicable to deterministic (nonrandom) testing. A fundamental problem of space compaction--how much aliasing-free compaction can be achieved for a given circuit, fault model, and test set--is solved using a new graph model. We establish an equivalence between graph coloring and the design of space compactor circuits. The formal theory leads to a systematic procedure for the synthesis of space compactors. It also leads to several parity-based space compaction methods that guarantee zero aliasing. A new BIST circuit called a multiplexed parity tree is presented that combines the error propagation properties of multiplexers and parity trees. We investigate time compaction using a functional property of the circuit under test called balance. We develop the theory of balance testing and present necessary and sufficient conditions for the detection of various fault types. Complete fault coverage can be achieved with balance testing using design for balance testability (DFBT). The key idea in DFBT is to place the circuit under test in a testable framework that guarantees complete balance testability. Time compaction of test responses from processor circuits can also be efficiently carried out using accumulators that are used for normal operation. We analyze the error coverage of accumulator-based compaction schemes using a novel probabilistic technique based on the central limit theorem of statistics. Finally, we investigate composite space-time compaction in which the space and time compaction steps are merged. This is in contrast to traditional compaction schemes that separately address compaction in the space and time dimensions. We exploit the fact that response verification is equivalent to the problem of recognizing a fault-free response sequence and develop a design technique for synthesizing low-cost sequence detectors for response compaction. Extensive simulations results on fault coverage and hardware overhead for the ISCAS 85 benchmark circuits are presented, which demonstrate that low-cost, aliasing-free response compaction can be easily achieved in BIST.PhDComputer Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/104754/1/9610091.pdfDescription of 9610091.pdf : Restricted to UM users only