Modeling CMOS for high-temperature applications.

The primary goals of this work have been to improve understanding of CMOS high-temperature effects and to generate models which accurately represent these effects. This research has demonstrated that properly designed silicon circuits can operate at temperatures to 300$\sp\circ$C. Experimental analysis of MOS transistors demonstrated the device effects which degrade CMOS performance with increasing temperature and restrict the temperature range of functionality. These effects are: the increase in leakage current, shift in threshold voltage, increase in subthreshold swing, decrease in carrier mobilities, and CMOS latchup. A more accurate model for the depletion-layer width of step junctions has been developed based on extensive simulation over the range of parameters of interest. One of the most important implications from the more accurate model is that small-signal junction capacitance has a higher value at high temperatures than that predicted by the complete-depletion approximation. This effect, combined with temperature-related mobility degradation makes it difficult for silicon electronic circuits to achieve high-temperature and high-speed operation concurrently. A more accurate MOS threshold voltage model (based on our depletion model), and a correction to the Fermi potential calculation have been incorporated into SPICE, so that it can be used for high-temperature circuit simulation. Complete characterization of latchup over temperature has been done on nine different processes. Epitaxial CMOS shows significantly better latchup performance than comparably processed bulk wafers, and can serve as efficient means for extending operating temperatures beyond that which bulk CMOS can support. This study has demonstrated that high-temperature circuits can, using more conservative design rules, take advantage of the process developments done to prevent latchup in dense, submicron VLSI processes. Silicon operation can be pushed to still higher temperatures through the use of silicon-on-insulator technologies. An empirical model of holding voltage, based on a conductivity-modulation model, is presented. This model can be used for adjusting the spacing between n- and p-active areas to achieve constant latchup immunity over temperature.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/102951/1/9023675.pdfDescription of 9023675.pdf : Restricted to UM users only