Towards minimizing the risks of soft errors at the design level of embedded systems

The risks of soft errors increase with system complexity, reduction in operational voltages, exponential growth in transistors per chip, increases in clock frequencies and device shrinking. Research into techniques to cope with soft errors has mostly focused on post-design phases such as circuit level solutions, logic level solutions, spatial redundancy, temporal redundancy, and/or error correction codes. Clearly, though, it would be better to tackle the issue early in the design process. A novel method is outlined in this research for assigning a criticality ranking to the components in a design at the conceptual phase. The ranking is easily derived with little computational effort. Further, the research flags why the component is critical. The model is then examined by refactoring to lower each component’s criticality until the goal of minimising the risks of soft errors is satisfied and constraints are maintained. The methodology is then tested against real-life systems that must have high reliability