LANE-BASED HARDWARE SPECIALIZATION FOR LOOP- AND FORK-JOIN-CENTRIC PARALLELIZATION AND SCHEDULING STRATEGIES

Serious physical design issues are breaking down traditional abstractions in computer architec- ture. For the past 40 years, Moore’s Law and Dennard’s Scaling have provided the smaller, cheaper, faster, and more power-efficient transistors that fueled innovation in computer architecture. In the mid 2000s, Dennard’s Scaling broke down, and this in turn stagnated the growth in processor clock frequencies and reduced the power efficiency of transistors. More recently, there has been empirical evidence suggesting Moore’s Law of transistor cost-scaling has slowed down. While transistors continue to shrink at a slower pace, technology scaling is no longer ensuring cheaper, faster, and more power-efficient transistors. In this disruptive regime, architects have a critical role in improving performance while mitigating design costs. The challenges posed by the impending end of Moore’s Law and the non-existent benefits of Dennard’s Scaling motivate reconsidering the traditional boundaries between hardware and software. Architects have responded by embracing parallelization and specialization across the layers of the computing stack. A key research challenge involves creating clean hardware/software abstractions that are highly programmable, yet still enable efficient execution on both traditional and specialized microarchitectures. In this thesis, I present a lane-based hardware specialization approach to building programmable accelerators for loop- and fork-join-centric parallel programs. To mitigate the design costs and in- crease the applicability of hardware specialization, I make the case for lane-based behavior-specific accelerators. I propose two lane-based behavior-specific accelerators: XLOOPS and SSAs. Explicit loop specialization (XLOOPS) is an approach that is based on the idea of elegantly encoding inter-iteration dependence patterns in the instruction set. The XLOOPS binaries can execute on (1) traditional microarchitectures with minimal performance impact, (2) specialized microarchitectures to improve performance and/or energy efficiency, and (3) adaptive microarchitectures that can seamlessly migrate loops between traditional and specialized execution to trade-off performance vs. energy efficiency. Smart sharing architectures (SSAs) are a new approach to building lane-based accelerators that can efficiently execute recursive fork-join-centric parallel programs. SSAs designs share expensive hardware resources to reduce the area costs and employ complexity- effective smart sharing mechanisms that exploit instruction redundancy to mitigate the loss in performance while maximizing efficiency