On the IC architecture and design of a 2 µm CMOS 8 MIPS digital signal processor with parallel processing capability: The PCB5010/5011

\u3cp\u3eA 2- mu m CMOS digital signal processor (PCB5010/PCB5011), capable of eight million instructions per second (8 MIPS) and up to six concurrent operations in each instruction is described. This high throughput results from a highly parallel architecture with high-speed data-handling capability. The processor contains two 16-b data buses, two primary execution units, five I/O interfaces, a data ROM, two data RAMs, and flexible addressing of on- and off-chip memory using three address computation units. Benchmarks show a two to six times improvement in overall performance over its predecessors.\u3c/p\u3