Characterization of thermal and electrical stability of MOCVD HfO \u3csub\u3e2\u3c/sub\u3e-HfSiO\u3csub\u3e4\u3c/sub\u3e dielectric layers with polysilicon electrodes for advanced CMOS technologies

\u3cp\u3eThe thermal and electrical stability of HfO\u3csub\u3e2\u3c/sub\u3e-HfSiO\u3csub\u3e4\u3c/sub\u3e dielectric layers with polysilicon electrodes are investigated in view of their use as gate dielectrics in advanced complementary metal oxide semiconductor (CMOS) technologies. The layers were deposited on 1 nm silicon oxide layers using metallorganic chemical vapor deposition (MOCVD). In situ p-doped polysilicon electrodes were deposited using rapid thermal chemical vapor deposition and low pressure chemical vapor deposition, respectively. The influence of rapid thermal annealing and postdeposition annealing of the high-k layers was investigated using MOS capacitors. The lowest equivalent oxide thickness was around 19.3 Å with a leakage current reduction of approximately 1000 times as compared to SiO\u3csub\u3e2\u3c/sub\u3e. MOSFETs fabricated using a standard direct gate etch approach were used to study the stability of the dielectric and device properties as functions of activation anneal and implant conditions. A major problem was found to be the stability of the threshold voltage V\u3csub\u3eT\u3c/sub\u3e. After 50 consecutive I\u3csub\u3ed\u3c/sub\u3e-V \u3csub\u3eg\u3c/sub\u3e dc sweeps from -1 to +2 V, the threshold voltage of n-MOS devices shifted 50-200 mV. Using pulsed I\u3csub\u3ed\u3c/sub\u3e-V\u3csub\u3eg\u3c/sub\u3e measurement technique, a hysteresis on the order of 300-400 mV was found. Only a minor improvement was achieved by different annealing of the layers. In conclusion, it was found that these layers exhibit unacceptably high instability to provide a solution as a gate dielectric for advanced CMOS technologies.\u3c/p\u3