Redundancy modelling and array yield analysis for repairable embedded memories

Embedded memories currently occupy more than 50% of the chip area for typical SOC integrated circuits. Defects in memory arrays can therefore significantly degrade manufacturing yield. In such a setting, repairable embedded memories are desirable because they help improve the memory array yield of an IC. We have developed an array yield analysis tool that provides realistic yield estimates for both single repairable memories, as well as for ICs containing multiple, possibly different, repairable embedded memories. Our approach uses pseudo-random fault bit-maps, which are generated based on memory area, defect density, and fault distribution. In order to accommodate a wide range of industrial memory and redundancy organizations, we have developed a flexible memory model. It generalizes the traditional simple memory matrix model with partitioning into regions, grouping of columns and rows, and column-wise and row-wise coupling of the spares. Our tool is used to determine an optimal amount of spare columns and rows for a given memory, as well as to determine the effectiveness of various repair algorithms