Embedded first-in first-out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded FIFO module with asynchronous read and write clocks, which is at least a factor two smaller and also faster than SRAM-based and standard-cell-based counterparts. The detection qualities of the FIFO test for both hard and weak resistive shorts and opens have been analyzed by an IFA-like method based on analog simulation. The defect coverage of the initial FIFO test for shorts in the bit-cell matrix has been improved by inclusion of an additional data background and low-voltage testing; for low-resistant shorts, 100% defect coverage is obtained. The defect coverage for opens has been improved by a new test procedure...
A FIFO is a special type of buffer that controls the data flow between the sender and receiver. It i...
This paper presents a comparative analysis of open (ADOF: Address Decoder Open Fault) and resistive ...
this paper presents several new asynchronous FIFO designs. While most existing FIFO’s have higher th...
NXP Semiconductors (formerly Philips Semiconductors) has created a new embedded asynchronous FIFO mo...
ABSTRACT: NXP Semiconductors (Philips Semiconductors) has created a new embedded asynchronous First-...
Embedded First-In First-Out (FIFO) memories are increasingly used in many IC designs. We have create...
Accordingly, the odds of run-time problems or defects occurring in buffers and logic are considerabl...
Aim of this paper is to present a self-testable FIFO memory macrocell, which can be embedded into la...
[[abstract]]Small delay defects, when escaping from traditional delay testing, could cause a device ...
Resistive defects in FinFET SRAMs are an important challenge for manufacturing test in submicron tec...
Journal ArticleHeterogeneous blocks, IP reuse, network-on-chip interconnect, and multi-frequency de...
In this thesis the importance of DFTs in the detection of DRFs in embedded SRAMs have been presented...
Manufacturing defects can cause faults in FinFET SRAMs. Of them, easy-to-detect (ETD) faults always ...
In the current scenario, with the increasing integration densities, most system-on-chip designs are ...
Abstract—With increasing inter-die and intra-die parameter variations in sub-100-nm process technolo...
A FIFO is a special type of buffer that controls the data flow between the sender and receiver. It i...
This paper presents a comparative analysis of open (ADOF: Address Decoder Open Fault) and resistive ...
this paper presents several new asynchronous FIFO designs. While most existing FIFO’s have higher th...
NXP Semiconductors (formerly Philips Semiconductors) has created a new embedded asynchronous FIFO mo...
ABSTRACT: NXP Semiconductors (Philips Semiconductors) has created a new embedded asynchronous First-...
Embedded First-In First-Out (FIFO) memories are increasingly used in many IC designs. We have create...
Accordingly, the odds of run-time problems or defects occurring in buffers and logic are considerabl...
Aim of this paper is to present a self-testable FIFO memory macrocell, which can be embedded into la...
[[abstract]]Small delay defects, when escaping from traditional delay testing, could cause a device ...
Resistive defects in FinFET SRAMs are an important challenge for manufacturing test in submicron tec...
Journal ArticleHeterogeneous blocks, IP reuse, network-on-chip interconnect, and multi-frequency de...
In this thesis the importance of DFTs in the detection of DRFs in embedded SRAMs have been presented...
Manufacturing defects can cause faults in FinFET SRAMs. Of them, easy-to-detect (ETD) faults always ...
In the current scenario, with the increasing integration densities, most system-on-chip designs are ...
Abstract—With increasing inter-die and intra-die parameter variations in sub-100-nm process technolo...
A FIFO is a special type of buffer that controls the data flow between the sender and receiver. It i...
This paper presents a comparative analysis of open (ADOF: Address Decoder Open Fault) and resistive ...
this paper presents several new asynchronous FIFO designs. While most existing FIFO’s have higher th...