A method for storing a vector of process data elements (D1, . . . , D8) that have a size of n bits from a register file (RF) into a memory (M) is described. The memory is arranged for storage of a vector of storage data elements in locations (M1, . . . , M5) having a size of m bits, wherein m>n. The method comprises the steps of: exchanging bits (S2) between process data elements in the vector stored in mutually subsequent register elements, the exchanging resulting in a vector of modified data elements (DmI, . . . , Dm8), shuffling (S3) groups of k subsequent bits in the resulting vector, --storing (S4) the resulting shuffled vector of modified data elements as a vector of storage data elements in the memory (M)
A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed...
Previous vector architectures divided the available register file space in a fixed number of registe...
The invention relates to a method for handling data (A, B) between two memory areas (W, R1, R2) of a...
A method for storing a vector of process data elements (D1, . . . , D8) that have a size of n bits f...
The invention discloses a data updating method, a storage space setting method and device, a chip an...
A memory architecture is presented. The memory architecture comprises a first memory and a second me...
Proceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engi...
Abstract—Previous vector architectures divided the available register file space in a fixed number o...
The storage requirements in data-dominated signal processing systems, whose behavior is described by...
[[abstract]]In this paper, we address the register file design with Single Instruction Multiple Data...
Processor register file (RF) is an important microarchitectural component used for storing operands ...
AbstractIn a processor architecture, the beauty of bus organization lies on the easy transferring of...
The invention concerns a data storage method enabling error detection and correction in an organized...
Abstract—In this paper, we present an efficient instruction set architecture using vector register f...
An apparatus and method for creation of reordered vectors from sequential input data for block based...
A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed...
Previous vector architectures divided the available register file space in a fixed number of registe...
The invention relates to a method for handling data (A, B) between two memory areas (W, R1, R2) of a...
A method for storing a vector of process data elements (D1, . . . , D8) that have a size of n bits f...
The invention discloses a data updating method, a storage space setting method and device, a chip an...
A memory architecture is presented. The memory architecture comprises a first memory and a second me...
Proceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engi...
Abstract—Previous vector architectures divided the available register file space in a fixed number o...
The storage requirements in data-dominated signal processing systems, whose behavior is described by...
[[abstract]]In this paper, we address the register file design with Single Instruction Multiple Data...
Processor register file (RF) is an important microarchitectural component used for storing operands ...
AbstractIn a processor architecture, the beauty of bus organization lies on the easy transferring of...
The invention concerns a data storage method enabling error detection and correction in an organized...
Abstract—In this paper, we present an efficient instruction set architecture using vector register f...
An apparatus and method for creation of reordered vectors from sequential input data for block based...
A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed...
Previous vector architectures divided the available register file space in a fixed number of registe...
The invention relates to a method for handling data (A, B) between two memory areas (W, R1, R2) of a...