A junction level study of the activation process in nanowire networks

Nanowire networks are promising memristive architectures for neuromorphic computing applications due to their connectivity and neurosynaptic-like behaviours. In this PhD thesis, we demonstrate a self-similar scaling 1 of the conductance of networks and the junctions that comprise them. As a result, we introduce a dynamic memristive model 2, based on tunnelling conduction, this model is capable of describing the growth of conductive filaments within the nanowire junctions and consequently the connectivity evolution of the networks. Through the interplay of experimental results and simulations, we demonstrate how a particular class of junctions leads to the emergence of conducting paths which we define as \u27winner-takes-all\u27 (WTA) paths. The emergence of these electrical paths is characterized by particular conductance plateaus and by the fact that they represent the most efficient way to transfer the information through networks. These results point to the possibility of independently addressing memory or conductance states in complex systems and is expected to have important implications for memory and neuromorphic computing devices