Towards a Full-Flexible and Fast-Prototyping TOF-PET Block Detector Based on TDC-on-FPGA

Typically, a time-of-flight (TOF) PET block detector is built using application-specific integrated circuits (ASICs), since they integrate a high number of channels at a reasonable power consumption and into a small area. However, ASICs’ flexibility is limited and prototyping times are long because a semiconductor fabrication process is required in every design iteration. Alternatively, fast terminal (FT) silicon photomultipliers (SiPMs) require a simplified analog front-end in order to achieve time-of-flight (TOF) accuracy. In addition, field-programmable gate arrays (FPGAs) can allocate time-to-digital converters (TDCs) as well as complex digital readout logics. In this work, we propose building TOF-PET block detectors based on FPGAs, FT-SiPMs, and minimal amount of off-the-shelf components. In this way, TOF-PET accuracy is achieved with a full-flexible and fast prototyping solution. We evaluated the coincidence resolving time (CRT), performance degradations due to channel multiplexing, energy resolution, and scintillator pixel encoding performance of SiPM arrays utilizing the proposed approach. Experimental results show minimal timing degradations, when multiplexing FTs. Moreover, simulation results show a low reduction in the singles count rate of multiplexed channels at typical brain-PET radioactive doses