Design and implementation of a constant-time FPGA accelerator for fast elliptic curve cryptography

Elliptic Curve Cryptography (ECC) is one of the most popular public-key cryptosystems (PKC) today. Relatively shorter key lengths used in ECC compared to other popular PKCs and its potential for faster and more e cient implementations, both in software and in hardware, make it popular in industry and academia. In this thesis, we propose a scalar multiplication hardware accelerator that computes a constant-time variable-base point multiplication over the Galbraith-Lin-Scott (GLS) family of binary elliptic curves. Our hardware design is speci cally customized for the quadratic extension eld F[22n]; with n = 127; which provides a security level close to 128 bits. We experiment with digit-based and Karatsuba multipliers for performing F[2127] arithmetic used in GLS elliptic curves and report the time and area performances obtained by these two classes of multipliers. The real hardware implementation of our design achieves a delay of about 3.98 s for computing one scalar multiplication on a XILINX KINTEX-7 FPGA device. This result clearly demonstrates that the proposed design claims the current speed record for this operation at or around the 128-bit security level for any hardware or software implementation reported in the literature