International audienceWe demonstrate the fabrication and electrical characterization of -gate Tunnel Field Effect Transistors (TFET) based on p-Si/i-Si/n+Si0.7Ge0.3 heterostructure nanowires grown by Chemical Vapor Deposition (CVD) using the vapor–liquid–solid (VLS) mechanism. The electrical performances of the p-Si/i-Si/n+Si0.7Ge0.3 heterostructure TFET device are presented and compared to Si and Si0.7Ge0.3 homostructure nanowire TFETs. We observe an improvement of the electrical performances of TFET with p-Si/i-Si/n+Si0.7Ge0.3 heterostructure nanowire (HT NW). The optimized devices present an Ion current of about 245 nA at VDS = −0.5 V and VGS = −3 V with a subthreshold swing around 135 mV/dec. Finally, we show that the electrical results...
Complementary MOSFET and Tunnel-FET inverters based on tri-gated strained Si nanowire arrays are dem...
This paper presents SiGe nanowire tunneling field effect transistors (TFETs) cointegrated with MOSFE...
In this letter, we systematically investigate the impact of gate length and channel orientation on t...
International audienceWe demonstrate the fabrication and electrical characterization of -gate Tunnel...
We demonstrate the fabrication and electrical characterization of Ω-gate Tunnel Field Effect Transis...
Guided by the Wentzel-Kramers-Brillouin approximation for band-to-band tunneling (BTBT), various per...
Reducing power consumption is an important issue for integrated circuits in portable devices relying...
In this letter, we systematically investigate the impact of gate length and channel orientation on t...
Reducing power consumption is an important issue for integrated circuits in portable devices relying...
This paper provides an experimental proof that both the ON-current ION and the subthreshold swing SS...
session 8: Beyond CMOSInternational audienceWe present for the first time high performance Nanowire ...
Different vertical nanowire heterojunction devices were fabricated and tested based on vertical Ge n...
This paper presents a new integration scheme to fabricate a Si/Si 0.55 Ge0.45 heterojunction line tu...
This paper presents optimization techniques for 20 nm channel length novel Si/SiGe heterojunction p-...
We present for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS...
Complementary MOSFET and Tunnel-FET inverters based on tri-gated strained Si nanowire arrays are dem...
This paper presents SiGe nanowire tunneling field effect transistors (TFETs) cointegrated with MOSFE...
In this letter, we systematically investigate the impact of gate length and channel orientation on t...
International audienceWe demonstrate the fabrication and electrical characterization of -gate Tunnel...
We demonstrate the fabrication and electrical characterization of Ω-gate Tunnel Field Effect Transis...
Guided by the Wentzel-Kramers-Brillouin approximation for band-to-band tunneling (BTBT), various per...
Reducing power consumption is an important issue for integrated circuits in portable devices relying...
In this letter, we systematically investigate the impact of gate length and channel orientation on t...
Reducing power consumption is an important issue for integrated circuits in portable devices relying...
This paper provides an experimental proof that both the ON-current ION and the subthreshold swing SS...
session 8: Beyond CMOSInternational audienceWe present for the first time high performance Nanowire ...
Different vertical nanowire heterojunction devices were fabricated and tested based on vertical Ge n...
This paper presents a new integration scheme to fabricate a Si/Si 0.55 Ge0.45 heterojunction line tu...
This paper presents optimization techniques for 20 nm channel length novel Si/SiGe heterojunction p-...
We present for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS...
Complementary MOSFET and Tunnel-FET inverters based on tri-gated strained Si nanowire arrays are dem...
This paper presents SiGe nanowire tunneling field effect transistors (TFETs) cointegrated with MOSFE...
In this letter, we systematically investigate the impact of gate length and channel orientation on t...