Assessment of technological device parameters by low-frequency noise investigation in SOI omega-gate nanowire NMOS FETs
- Koyama, M.
- Cassé, M.
- Barraud, S.
- Ghibaudo, G.
- Iwai, H.
- Reimbold, G.
Publication date
April 2014
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE)Abstract
session 5: Device CharacterizationInternational audienceWe report an experimental investigation of oxide/channel interface quality in SOI omega-gate nanowire NMOS FETs with cross-section as small as 10nm×10nm by low-frequency noise measurements. The noise study has been efficiently applied for the characterization of various technological parameters, including strained channel, H 2 anneal, or channel orientation. A method for rigorous contribution assessment of the two interfaces (top surface vs. side-walls) is also demonstrated. Excellent quality of the interfaces is extracted for all our technological and structural parameters
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