Performance and Reliability of a Fully Integrated 3D Sequential Technology
- Tsiara, A.
- Garros, X.
- Brunet, L.
- Batude, P.
- Fenouillet-Beranger, C.
- Triantopoulos, K.
- Cassé, M.
- Vinet, M.
- Gaillard, F.
- Ghibaudo, G.
Publication date
June 2018
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE)Abstract
session T7: Process and Material TechnologyInternational audienceWe investigate in detail, for the first time, both performance and reliability of a 3D sequential integration process. It is clearly demonstrated that the top level transistor can be successfully processed at 630°C with almost no impact on the performance and reliability of the bottom level. It is also highlighted that top level devices meet the P&NBTI reliability requirements. Finally an example of successful and robust 3D logic integration is proposed based on a 3D inverter combining a top-level PMOS with a bottom-level NMOS
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