Effects of digital switching noise on analog voltage references in mixed-signal CMOS ICs

In this paper we present an approach to analyze effects of digital switching noise on sensitive nodes of the analog section in mixed analog/digital CMOS integrated circuits. As well known, a pre-layout estimation of digital switching noise is a very important target in mixed-signal system-on-chip design. To speed up simulation time, we analyzed the digital and the analog section separately. Digital switching current are evaluated using a dedicated simulation algorithm, while propagation of digital disturbances and their effects on analog blocks are simulated with SPICE. The flexibility of this approach allows us to evaluate the effects of package parasitics, of different switching noise amplitudes, and of different current pulse durations on the same analog circuit, while keeping computational cost and simulation time at low levels. The proposed case study is represented by a flash ADC, acting as analog noise collector, and a set of disturbances due to the current consumption of a two phase clock generator, acting as digital noise generator