Improving Power, Performance and Area with Test: A Case Study

As more low power devices are needed for applications such as Internet of Things, reducing power and area is becoming more critical. Reducing power consumption and area caused by full scan design-for-test should be considered as a way to help achieve these stricter requirements. This is especially important for designs that use near-threshold technology. In this work, we use partial scan to improve power, performance and area on a graphics processing unit shader block. We present our non-scan D flip-flop (DFF) selection algorithm that maximizes non-scan DFF count while achieving automatic test pattern generation results close to those of the full scan design. We identify a category of stuck-at faults that are unique to partial scan designs and propose a check to identify and contain them. Our final test coverage of the partial scan design is within 0.1% of the full scan test coverage for both stuck-at and transition delay fault models. In addition, we present the PPA (power, performance and area) results for both the full scan and partial scan designs. The most noteworthy improvement is seen in the hold total negative slack