session D: SoC, DFM.TCADInternational audienceThis paper presents a new device named the Gated Diode merged BIMOS (GDBIMOS) which is fabricated using the 28nm UTBB FD-SOI high-k metal gate CMOS technology. It is highly reconfigurable and topologically robust for ESD protection. The suitable ESD window is achieved thanks to doping adjustment and to different possible gate connections
Abstract—An electrostatic discharge (ESD) protection design for smart power applications with latera...
A novel layout strategy for on-chip ESD protection application is presented to solve the non-uniform...
session J: I/O circuits and ESD protectionInternational audienceThe purpose of this paper is to anal...
session D: SoC, DFM.TCADInternational audienceThis paper presents a new device named the Gated Diode...
session 7: CharacterizationInternational audienceGDNMOS (Gated Diode merged NMOS) and GDBIMOS (Gated...
session 11: Advanced DevicesInternational audienceWe propose a novel device (GDNMOS: Gated Diode mer...
International audienceWe propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fab...
International audienceWe evaluate the Electro-Static Discharge (ESD) protection capability of BIpola...
International audienceUltrathin bipolar + MOS (BiMOS) transistors were fabricated with 28-nm Ultra T...
session 2: POwer Devices and ESD ProtectionInternational audienceThe purpose of this study is to eva...
session: Power ManagementInternational audienceWe investigate the impact of carrier mobility on the ...
International audienceIn this paper, we introduce a new BIMOS transistor fabricated with 28nm high-k...
The electrostatic discharge (ESD) protection is a major concern for advanced CMOS technology manufac...
L’architecture FDSOI (silicium sur isolant totalement déserté) permet une amélioration significative...
Abstract—An electrostatic discharge (ESD) protection design for smart power applications with latera...
A novel layout strategy for on-chip ESD protection application is presented to solve the non-uniform...
session J: I/O circuits and ESD protectionInternational audienceThe purpose of this paper is to anal...
session D: SoC, DFM.TCADInternational audienceThis paper presents a new device named the Gated Diode...
session 7: CharacterizationInternational audienceGDNMOS (Gated Diode merged NMOS) and GDBIMOS (Gated...
session 11: Advanced DevicesInternational audienceWe propose a novel device (GDNMOS: Gated Diode mer...
International audienceWe propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fab...
International audienceWe evaluate the Electro-Static Discharge (ESD) protection capability of BIpola...
International audienceUltrathin bipolar + MOS (BiMOS) transistors were fabricated with 28-nm Ultra T...
session 2: POwer Devices and ESD ProtectionInternational audienceThe purpose of this study is to eva...
session: Power ManagementInternational audienceWe investigate the impact of carrier mobility on the ...
International audienceIn this paper, we introduce a new BIMOS transistor fabricated with 28nm high-k...
The electrostatic discharge (ESD) protection is a major concern for advanced CMOS technology manufac...
L’architecture FDSOI (silicium sur isolant totalement déserté) permet une amélioration significative...
Abstract—An electrostatic discharge (ESD) protection design for smart power applications with latera...
A novel layout strategy for on-chip ESD protection application is presented to solve the non-uniform...
session J: I/O circuits and ESD protectionInternational audienceThe purpose of this paper is to anal...