Silicon tunnel FET with average subthreshold slope of 55mV/dec at low drain currents
- Narimani, K.
- Glass, S.
- Rieger, T.
- Bernardy, P.
- von den Driesch, N.
- Mantl, S.
- Zhao, Q. T.
Publication date
January 2017
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE)Abstract
In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. It is shown that the device achieves I on /I off ratio of 5×10 4 considering I on (V on = V Ioff -0.5V) = 0.8×10 -8 μA/μm and an average SS of 55mV/dec over two orders of magnitude of I d . Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency g m /I d beats the MOSFET performance at lower currents
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