SiGe based line tunneling field-effect transistors

In this paper we report on our progress with SiGe gate-normal / line tunneling FETs, highlighting recent advancements by the example of three transistor concepts. We demonstrate the unique characteristics shared by these transistors, such as the on-current proportionality to the source-gate-channel overlap area and explain the obstacles imposed by fringing fields leading to parasitic tunneling at the edges of the tunneling area. Our experimental results show that adding counter doping to the channel provides an efficient means to mitigate penalties to the subthreshold swing caused by parasitic tunneling paths and additionally helps to improve the on-current and Ion/Ioff-ratio. Moreover, we point out the dependence of the superlinear onset on the tunneling transmission probability with a focus on the doping profile at the tunneling junction. We consider the role of traps on the subthreshold swing within the scope of temperature dependent electrical measurements. Furthermore, we show that by avoiding ion implantation and hence crystal defects as much as possible, smaller minimum subthreshold swings can be reached. At last, taking the experience acquired on the three transistors concepts into consideration, we propose an advanced TFET concept