Active-precharge hammering on a row induced failure in DDR3 SDRAMs under 3�� nm technology

This paper introduces the new failure mechanism manifested in DDR3 SDRAMs under 3�� nm technology. The failure in normal cells is caused by iterative hammering accesses to a row within a refresh cycle. With the valid yet stressful access to a row, the charge in a DRAM cell leaked faster and the values of the stressed cells could not be retained. The three test parameters - tRP, data pattern, and temperature-were varied during the row hammering experiments to understand the contributions of each in triggering and accelerating the failing mechanisms. Here, we mainly discuss the experimental results of the commercial DDR3 components from three major memory vendors. All commercial DDR3 components failed much earlier than the specified limit of allowed accesses. For a vendor memory component, a cell started to fail after only 98K accesses to a row, which is about 7.54% of the specification-permitted accesses of 1,300K �� 2014 IEEE