In this experiment, metal (Mo/Cu) seed layers with an aspect ratio of 10:1 were deposited by a conventional sputtering method and then copper filling by electroplating was followed in order to fabricate through silicon vias with a high aspect ratio. With increasing the aspect ratio, it is critical to carefully control the reduction of via's hole size before filling the bottom seed layer. By changing sputtering time, pressure, and power, changes in the thickness of the metal seed layers were investigated. It was found that optimizing the sputtering conditions improved the quality of the seed layer and retarded the speed of the hole size reduction. As a result, a metal seed layer with a via's opening percentage of about 62% and a bottom seed ...
Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced ...
In this study, the filling process of high aspect ratio through-silicon-vias (TSVs) under dense cond...
In this study, the filling process of high aspect ratio through-silicon-vias (TSVs) under dense cond...
There is an increasing demand for electronic devices with smaller sizes, higher performance and incr...
The paper addresses the through silicon via (TSV) filling using electrochemical deposition (ECD) of ...
La miniaturisation nécessaire à l'accroissement des performances des composants microélectroniques e...
International audienceIn order to anticipate the further demands of miniaturization and integration ...
To overcome the limitation of the sputtered Cu seed layer in electroplating of Cu interconnects impo...
In order to realize low resistance through-Si via (TSV) electrodes, Cu electroplating is one of the ...
To overcome the limitation of the sputtered Cu seed layer in electroplating of Cu interconnects impo...
The background of this paper is the fabrication of Through Silicon Vias (TSV) for three-dimensional ...
International audienceIn order to anticipate the further demands of miniaturization and integration ...
International audienceIn order to anticipate the further demands of miniaturization and integration ...
Interconnects are significant elements in integrated circuits (ICs), as they connect individual comp...
Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced ...
Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced ...
In this study, the filling process of high aspect ratio through-silicon-vias (TSVs) under dense cond...
In this study, the filling process of high aspect ratio through-silicon-vias (TSVs) under dense cond...
There is an increasing demand for electronic devices with smaller sizes, higher performance and incr...
The paper addresses the through silicon via (TSV) filling using electrochemical deposition (ECD) of ...
La miniaturisation nécessaire à l'accroissement des performances des composants microélectroniques e...
International audienceIn order to anticipate the further demands of miniaturization and integration ...
To overcome the limitation of the sputtered Cu seed layer in electroplating of Cu interconnects impo...
In order to realize low resistance through-Si via (TSV) electrodes, Cu electroplating is one of the ...
To overcome the limitation of the sputtered Cu seed layer in electroplating of Cu interconnects impo...
The background of this paper is the fabrication of Through Silicon Vias (TSV) for three-dimensional ...
International audienceIn order to anticipate the further demands of miniaturization and integration ...
International audienceIn order to anticipate the further demands of miniaturization and integration ...
Interconnects are significant elements in integrated circuits (ICs), as they connect individual comp...
Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced ...
Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced ...
In this study, the filling process of high aspect ratio through-silicon-vias (TSVs) under dense cond...
In this study, the filling process of high aspect ratio through-silicon-vias (TSVs) under dense cond...