A Process-Aware Hot/Cold Identification Scheme for Flash Memory Storage Systems

NAND flash memory has attractive features compared to hard disk drives such as small size, no mechanical noise and shock resistance. But it also has some drawbacks such as no support for in-place updates and limited program/erase cycles, which trigger the development of sophisticated buffer management algorithms in order to reduce write and/or erase operations to flash memory. The significant gap in update frequency between hot and cold data motivates us to separate hot and cold data on different flash blocks to avoid unnecessary program/erase cycles. Many buffer management algorithms determine a request to be hot or cold based on its requested data size. However, the data size could become a wrong indicator of update frequency in many applications. In this paper, we propose a new hot/cold identification scheme in order to increase identification accuracy and, thus, to enhance storage performance and durability by reducing program/erase cycles. The proposed technique uses the process identification used in many operating systems as a hot/cold indicator. The experimental results show that the proposed scheme contributes to high performance and durability as compared to previously proposed identification schemes(1).This work was supported by the Brain Korea 21 Project in 2010. This research paper also has been supported by Nano IP/SoC Promotion Group of Seoul R&BD Program (10560) in 2010. This paper was funded by the New IT Project for global competitiveness strengthening of the advanced mobile devices and equipments of the Chungcheong Leading Industry Office of the Korean Ministry of Knowledge Economy