Time-Multiplexed 1687-Network for Test Cost Reduction

The reconfigurable scan network standardized by IEEE std. 1687 offers flexibility in accessing the on-chip instruments, which significantly improves the test cost. In this paper, we present a novel time-multiplexed 1687-network architecture that significantly improves the absolute test application time of systems-on-chip at wafer-level as well as package-levels tests. This architecture leverages: 1) the ever increasing tester channel frequency; 2) the allowed test frequencies at the two test levels; and 3) the flexibility offered by the 1687-network. We also present a test-time calculation method for the proposed network architecture and use it in our experiments. Furthermore, we study the effects of the number of time slots on different parameters.This work was supported in part by the Higher Education Commission, Govt. of Pakistan, under the scholarship program titled "Faculty Development of UESTPs/UETs," in part by the National Research Foundation of Korea Grant through the Ministry of Education, Science and Technology under Grant NRF-2017R1D1A1B03030821, in part by the Ministry of Trade, Industry and Energy under Grant 10052875, and in part by the Korea Semiconductor Research Consortium support program for the development of the future semiconductor device. This paper was recommended by Associate Editor S. Patil. (Corresponding author: Muhammad Adil Ansari.