Position Shift Analysis in Resist Reflow Process for Sub-50 nm Contact Hole

Contact hole (CH) patterning, especially for the sub-50 nm node, is one of the most difficult techniques in optical lithography. The resist reflow process (RRP) can be used to obtain smaller CHs. RRP is a simple technique in which the resist, after the development process, is baked above the glass transition temperature. Heating causes resist flow, and smaller CHs can be obtained. However, RRP is an unmanageable method because of the CH offset caused by the pattern position in random array CHs. Thus we tried optical proximity correction to find a uniform critical dimension (CD) for every CH, and we obtained uniform CDs for every CH after RRP. However, we still have a CH position shift problem. Because of the difference in the amount of resist that flows into the hole in a random array during the reflow process, position shift occurs. This position shift causes an overlay error, which may exceed the overlay error budget suggested in the ITRS roadmap. In this work, we try to determine not only uniform CID size of each CH, but also the optimum conditions for correcting CH position shift by homemade simulation. Moreover, we checked the behavior of CH position shift by e-beam lithography. Consequently, we confirmed that CHs shifted in a receding direction from each other, and obtained sub-50 nm CHs in a random array by considering the position shift by simulation and experiment. (C) 2009 The Japan Society of Applied PhysicsThis work was supported by the Korea Research Foundation Grant funded by the Korean Government (MOEHRD, Basic Research Promotion Fund; KRF-2007-521-D00286)